The invention relates to a high frequency timing generator which is capable of producing an output timing pulse signal having a selectable frequency and reference phase.
The operation of a digital computer requires a number of sequences of timing pulses which typically bear a fixed relationship to one another. To increase the speed of operation of the computer, the output frequency of the pulse generators used to produce such timing sequences must be correspondingly increased, both to provide higher frequency sequences of timing pulses and also to provide short delay times between different sequences of such pulses. Similarly, systems used to test logic and memory circuits require high-speed operation for purposes of development and manufacturing.
FIG. 1 is a block diagram showing a prior art programmable timing generator of the same general type to which the invention pertains. The output of a clock source 11 is applied to the CLOCK input of a counter 12. The binary count output bits of the counter 12 are applied to corresponding input bits of a first input port of a comparator 13, the second input port of which receives a digital timing pulse interval control word B=B.sub.N 2.sup.N +. . . +B.sub.1 2.sup.1 +B.sub.0 2.sup.0. The comparison output from the comparator 13 is applied to one input of an AND gate 14, the other input of which receives the output from the clock source 11. The output of the AND gate 14 is applied to the RESET input of the counter 12, and also forms the output timing pulse signal on a line 15.
In operation, the digital word inputted to the second input port of the comparator 13 is set to a value which corresponds to the desired output timing pulse interval. When the output of the counter 12 becomes equal to this value, the output of the comparator 13 becomes a logical 1. Thereupon, the AND gate 14 passes a single pulse of the clock signal to the line 15, which also resets the counter 12. The counter 12 then begins its count again from zero, and another timing pulse is generated when the output of the counter 12 again becomes equal to the value of the data word applied to the second input port of the comparator 13.
Chang et al. in IBM Technical Disclosure Bulletin, Vol. 20, No. 3, August 1977, p. 1027, disclose a programmable timing generator capable of operating at frequencies up to about 200 MHz. This sytem has a cycle time which is continuously programmable from five to 2,500 nsec. with the time delay for a particular sequence of pulses being programmable from zero to this cycle time. A reference timing pulse is generated by comparison of the output of a digital frequency counter with a set of reference control bits using an exclusive-OR circuit. The counter is reset by the reference timing pulse, and the counting sequence then restarted. Within the period of the reference timing pulse, a delayed pulse is generated by comparing the frequency counter output with a set of delay control bits, again using an exclusive-OR circuit. Variable delays of less than 20 nanoseconds are produced by gating the delayed pulse with a synchronous fine delay pulse.
In both of the above-described prior art programmable timing generators, the maximum frequency of the output timing pulses is restricted by the necessity of having to reset the counter each time a comparison is reached. That is, the resetting operation of a counter is a relatively slow operation, and limits the maximum frequency at which the generator can be operated.
Parsons et al. in U.S. Pat. No. 4,321,687 disclose a computer-controlled timing system in which the content of a series of shift registers is compared with a plurality of reference control bits (mask sets) stored in the computer. The shift registers contain an initial computer-loaded pattern which is advanced through a series of registers with timing pulses from a clock pulse generator using well-known shift register techniques. After each clock pulse, the bit pattern contained in the shift registers is compared sequentially with each bit of the mask set, and a pulse is generated each time a coincidence is detected between the two patterns. The speed of this system is limited by the requirement that after each clock pulse the content of the shift registers must be transferred to a set of storage registers, a mask fetched from storage, and the sequential comparisons made, all under the control of a computer.
It is an object of the present invention to provide a timing pulse generator which is not limited in frequency like the above-mentioned prior art programmable timing generators. Specifically, it is an object of the invention to provide a programmable timing pulse generator which can operate at frequencies of 500 MHz or higher using currently available components.